<?xml version="1.0" encoding="UTF-8"?><rss version="2.0" xmlns:content="http://purl.org/rss/1.0/modules/content/"><channel><title>Daedaleus</title><description>Personal Site</description><link>https://daedaleus.vercel.app/</link><language>en</language><item><title>FPGAs vs LEGOs</title><link>https://daedaleus.vercel.app/posts/fpga/fpgas_vs_legos/</link><guid isPermaLink="true">https://daedaleus.vercel.app/posts/fpga/fpgas_vs_legos/</guid><description>Introduction to FPGAs and Vivado Tool Flow</description><pubDate>Tue, 16 Jul 2024 00:00:00 GMT</pubDate><content:encoded>&lt;h1&gt;Table of Content&lt;/h1&gt;
&lt;ol&gt;
&lt;li&gt;&lt;a href=&quot;#introduction&quot;&gt;Introduction&lt;/a&gt;&lt;/li&gt;
&lt;li&gt;&lt;a href=&quot;#tool-flows&quot;&gt;Tool Flows&lt;/a&gt;
&lt;ol&gt;
&lt;li&gt;&lt;a href=&quot;#starting-ip-vivado&quot;&gt;Starting Vivado&lt;/a&gt;&lt;/li&gt;
&lt;li&gt;&lt;a href=&quot;#starting-up-vitis&quot;&gt;Starting Vitis&lt;/a&gt;&lt;/li&gt;
&lt;li&gt;&lt;a href=&quot;#programming-with-vitis&quot;&gt;Programming with Vitis&lt;/a&gt;&lt;/li&gt;
&lt;li&gt;&lt;a href=&quot;#programming-with-pynq&quot;&gt;Programming with PYNQ&lt;/a&gt;&lt;/li&gt;
&lt;/ol&gt;
&lt;/li&gt;
&lt;/ol&gt;
&lt;h1&gt;Introduction&lt;/h1&gt;
&lt;p&gt;&amp;lt;p&amp;gt;
LEGOs, the age old pastime of kids around the world and the age old torture device of people unlucky enough to step on them with bare feet.
&amp;lt;/p&amp;gt;&lt;/p&gt;
&lt;p&gt;&amp;lt;p&amp;gt;
So what can LEGOs teach us about digital electronics. A lot actually. FPGAs are nothing but a bunch of digital LEGO bricks waiting to be connected to each other. Except in FPGAs these bricks/components are called LUTs or Look Up Tables. &amp;lt;/p&amp;gt;&lt;/p&gt;
&lt;p&gt;&amp;lt;p&amp;gt;
These LUTs are programable cells that can be configured to perform a certain function like AND, OR etc. So essentially giving our bricks the superpower to change shape based on our requirements!
&amp;lt;/p&amp;gt;&lt;/p&gt;
&lt;p&gt;&amp;lt;p&amp;gt;
This level of programmability allows anyone with sufficient knowledge and patience to implement almost any digital circuit or system you can imagine. This allows for rapid prototyping and testing any circuit. Therefore an FPGA implementation is done before an ASIC (Application-specific integrated circuit) implementation.
&amp;lt;/p&amp;gt;&lt;/p&gt;
&lt;h1&gt;Tool Flows&lt;/h1&gt;
&lt;p&gt;&amp;lt;p&amp;gt;
Now let&apos;s talk about how we assemble these LUTs. Unlike a the physical bricks of LEGO, which we can put together with our hands, we need to use specialized EDA (Electronic Design Automation) tools to do this for us. Enter Vivado.
&amp;lt;/p&amp;gt;&lt;/p&gt;
&lt;p&gt;&lt;img src=&quot;./Xilinx_Development_Flow.png&quot; alt=&quot;Development Flows&quot; /&gt;&lt;/p&gt;
&lt;h3&gt;Starting up Vivado&lt;/h3&gt;
&lt;ol&gt;
&lt;li&gt;
&lt;p&gt;To start Vivado type the following by replacing install_path and version&lt;/p&gt;
&lt;pre&gt;&lt;code&gt;source &amp;lt;install_path&amp;gt;/Vivado/&amp;lt;version&amp;gt;/settings64.sh 
vivado
&lt;/code&gt;&lt;/pre&gt;
&lt;/li&gt;
&lt;li&gt;
&lt;p&gt;After Vivado starts up, you will see the Start Page. This screen provides several options:&lt;/p&gt;
&lt;ul&gt;
&lt;li&gt;
&lt;p&gt;&lt;strong&gt;Create New Project&lt;/strong&gt;: Opens the New Project wizard to create a new project&lt;/p&gt;
&lt;/li&gt;
&lt;li&gt;
&lt;p&gt;&lt;strong&gt;Open Project&lt;/strong&gt;: Opens a file browser to select an existing Xilinx Project (.xpr) file- &lt;strong&gt;Open Example Project&lt;/strong&gt;: Guides you through creating a new project based on an example project&lt;/p&gt;
&lt;/li&gt;
&lt;li&gt;
&lt;p&gt;&lt;strong&gt;Open Hardware Manager&lt;/strong&gt;: Opens the Hardware Manager without an associated project&lt;/p&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li&gt;
&lt;p&gt;To create a new project, click on &quot;Create New Project&quot; in the Quick Start panel. This will open the New Project dialog.&lt;/p&gt;
&lt;/li&gt;
&lt;li&gt;
&lt;p&gt;Follow the steps in the New Project wizard to specify the project name, location, project type (RTL Project), add sources if available, select the target board or device, and finish creating the project&lt;/p&gt;
&lt;/li&gt;
&lt;/ol&gt;
&lt;h3&gt;Starting up Vitis&lt;/h3&gt;
&lt;ol&gt;
&lt;li&gt;
&lt;p&gt;To launch Vitis on your local machine, open a terminal and run the following commands:&lt;/p&gt;
&lt;pre&gt;&lt;code&gt;source &amp;lt;install_path&amp;gt;/Vitis/2020.1/settings64.sh vitis
&lt;/code&gt;&lt;/pre&gt;
&lt;p&gt;This will launch the Vitis IDE. Alternatively, if Vivado is already open, you can launch Vitis through the Tools → Launch Vitis toolbar option.&lt;/p&gt;
&lt;/li&gt;
&lt;li&gt;
&lt;p&gt;When Vitis launches, you will be prompted to select a workspace, which is the directory where your projects and files will be stored. Choose an empty folder or create a new one.&lt;/p&gt;
&lt;/li&gt;
&lt;li&gt;
&lt;p&gt;The Vitis IDE provides a graphical user interface to create new application projects, add hardware functions, build the design, and run software and hardware emulation.&lt;/p&gt;
&lt;/li&gt;
&lt;li&gt;
&lt;p&gt;Vitis also supports a command-line flow where the user manages the compilation of host code and kernels using makefiles.&lt;/p&gt;
&lt;/li&gt;
&lt;li&gt;
&lt;p&gt;Vitis provides access to free comprehensive training courses and Vitis accelerated libraries for domain-specific and common libraries that are open-source and performance-optimized.&lt;/p&gt;
&lt;/li&gt;
&lt;/ol&gt;
&lt;h3&gt;Programming with Vitis&lt;/h3&gt;
&lt;ol&gt;
&lt;li&gt;
&lt;p&gt;&lt;strong&gt;Vivado Board Flow&lt;/strong&gt;:&lt;/p&gt;
&lt;ul&gt;
&lt;li&gt;Vivado is used to generate a custom .xsa file that is ported into Vitis as a platform project&lt;/li&gt;
&lt;li&gt;Developers can create a custom Vitis platform if they require a different set of physical PL I/O peripherals than those provided in AMD generated platforms.&lt;/li&gt;
&lt;li&gt;Vivado provides board files that automate the configuration of SOM-based peripherals for Kria boards like the K26 and K24 SOMs.&lt;/li&gt;
&lt;li&gt;The Vivado board files are available in the XHUB store or can be manually downloaded from the board store repo or kria-vitis-platforms repo.&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li&gt;
&lt;p&gt;&lt;strong&gt;Vitis Platform Flow&lt;/strong&gt;:&lt;/p&gt;
&lt;ul&gt;
&lt;li&gt;Developers use Vivado to generate a custom .xsa file to be ported into Vitis as a platform project&lt;/li&gt;
&lt;li&gt;Once the platform project is created in Vitis, a corresponding device tree overlay (.dtbo) is generated.&lt;/li&gt;
&lt;li&gt;With the .xsa and .dtbo files, developers can follow the Vitis Accelerator flow to create the final bitstream (.bit.bin), xclbin, and .dtbo files.&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ol&gt;
&lt;h3&gt;Programming with PYNQ&lt;/h3&gt;
&lt;p&gt;The recommended programming flows for PYNQ are:&lt;/p&gt;
&lt;ol&gt;
&lt;li&gt;Using Jupyter notebooks and Python code to load overlays and interact with the hardware&lt;/li&gt;
&lt;li&gt;Using Vivado to generate the hardware platform and Vitis to build the application, following examples like &lt;a href=&quot;https://github.com/Xilinx/PYNQ-HelloWorld&quot;&gt;PYNQ-HelloWorld&lt;/a&gt;&lt;/li&gt;
&lt;/ol&gt;
&lt;p&gt;::github(repo=&quot;Daedalus-op/summer-with-chips&quot;)&lt;/p&gt;
</content:encoded></item><item><title>Hardware Acceleration on an FPGA</title><link>https://daedaleus.vercel.app/posts/fpga/hardware-acceleration-on-an-fpga/</link><guid isPermaLink="true">https://daedaleus.vercel.app/posts/fpga/hardware-acceleration-on-an-fpga/</guid><description>A project on FPGA acceleration for AI applications</description><pubDate>Mon, 17 Jun 2024 00:00:00 GMT</pubDate><content:encoded>&lt;h1&gt;Abstract&lt;/h1&gt;
&lt;p&gt;This is a post to document our project on an FPGA board. We are going to use an FPGA board to accelerate the training of a KNN ML model.&amp;lt;br&amp;gt;&lt;/p&gt;
&lt;h1&gt;Progress&lt;/h1&gt;
&lt;ol&gt;
&lt;li&gt;[ ] Research
&lt;ul&gt;
&lt;li&gt;[x] KRIA KR260 Robotics Starter Kit&lt;/li&gt;
&lt;li&gt;[ ] hls4ml python package&lt;/li&gt;
&lt;li&gt;[ ] QKeras (supported by hls4ml)&lt;/li&gt;
&lt;li&gt;[x] Under the hood working of KNNs&lt;/li&gt;
&lt;li&gt;[x] Parts for optimization in a KNN model&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li&gt;[ ] Coding&lt;/li&gt;
&lt;li&gt;[ ] Testing&lt;/li&gt;
&lt;li&gt;[ ] Application&lt;/li&gt;
&lt;/ol&gt;
&lt;h1&gt;Part 1&lt;/h1&gt;
&lt;h2&gt;SOM Specs&lt;/h2&gt;
&lt;ul&gt;
&lt;li&gt;Components
&lt;ul&gt;
&lt;li&gt;SOM&lt;/li&gt;
&lt;li&gt;Carrier card&lt;/li&gt;
&lt;li&gt;Thermal solution&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li&gt;Zynq™ UltraScale+™ MPSoC EV (XCK26)&lt;/li&gt;
&lt;li&gt;4GB [non-ecc] DDR4&lt;/li&gt;
&lt;li&gt;I/O expansions
&lt;ul&gt;
&lt;li&gt;x4 Pmod 12-pin interface&lt;/li&gt;
&lt;li&gt;x1 Raspberry Pi HAT header with 26 I/Os&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li&gt;x4 USB 3.0/2.0 interfaces&lt;/li&gt;
&lt;/ul&gt;
&lt;h2&gt;Current development flow&lt;/h2&gt;
&lt;p&gt;&lt;img src=&quot;./Development_Flow.png&quot; alt=&quot;Hopefully!!!&quot; /&gt;&lt;/p&gt;
&lt;h2&gt;Parts to optimize&lt;/h2&gt;
&lt;ul&gt;
&lt;li&gt;Distance calculation types
&lt;ul&gt;
&lt;li&gt;Euclidean&lt;/li&gt;
&lt;li&gt;Manhattan&lt;/li&gt;
&lt;li&gt;Chebyshev&lt;/li&gt;
&lt;li&gt;Minowski&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li&gt;Sorting wrt distance and picking 1st K points&lt;/li&gt;
&lt;li&gt;Voting
&lt;ul&gt;
&lt;li&gt;Standard - Equal scheme&lt;/li&gt;
&lt;li&gt;Weighted scheme&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;/ul&gt;
&lt;h1&gt;Links&lt;/h1&gt;
&lt;h3&gt;Part 1&lt;/h3&gt;
&lt;ul&gt;
&lt;li&gt;&lt;a href=&quot;https://www.hackster.io/512359/amd-pervasive-ai-developer-contest-robotics-ai-study-guide-ae74d6&quot;&gt;KRIA SOM specs&lt;/a&gt;&lt;/li&gt;
&lt;li&gt;&lt;a href=&quot;https://www.xilinx.com/support/documents/sw_manuals/xilinx2022_2/ug1137-zynq-ultrascale-mpsoc-swdev.pdf&quot;&gt;Zynq UltraScale+ MPSoC: Software Developers Guide&lt;/a&gt;&lt;/li&gt;
&lt;li&gt;&lt;a href=&quot;https://www.xilinx.com/publications/events/developer-forum/2018-frankfurt/fundamentals-of-fpga-based-acceleration.pdf&quot;&gt;AMD fundamentals of FPGA acceleration&lt;/a&gt;&lt;/li&gt;
&lt;li&gt;&lt;a href=&quot;https://www.linkedin.com/pulse/unlocking-power-fpga-based-acceleration-aiml-dakshita-l-vwzmc/&quot;&gt;Scope of FPGA acceleration&lt;/a&gt;&lt;/li&gt;
&lt;li&gt;&lt;a href=&quot;https://zenseact.com/thinking-fast-and-getting-it-right-software-company-zenseact-and-cern-wrap-up-joint-research-project-around-the-acceleration-of-deep-learning-algorithms/&quot;&gt;Application of CV on FPGA - CERN&lt;/a&gt;&lt;/li&gt;
&lt;li&gt;&lt;a href=&quot;https://www.geeksforgeeks.org/k-nearest-neighbours/&quot;&gt;Fundamentals of KNN&lt;/a&gt;&lt;/li&gt;
&lt;li&gt;&lt;a href=&quot;https://medium.com/swlh/under-the-hood-of-k-nearest-neighbors-knn-and-popular-model-validation-techniques-84ab0964d563&quot;&gt;Under the hood for KNN models&lt;/a&gt;&lt;/li&gt;
&lt;li&gt;&lt;a href=&quot;https://medium.com/@sorenlind/nearest-neighbors-with-keras-and-coreml-755e76fedf36&quot;&gt;KNN on Keras&lt;/a&gt;&lt;/li&gt;
&lt;li&gt;&lt;a href=&quot;https://github.com/google/qkeras/issues/1&quot;&gt;Converting Keras to QNN&lt;/a&gt;&lt;/li&gt;
&lt;li&gt;&lt;a href=&quot;https://habana.ai/blogs/explore-hardware-acceleration-for-deep-learning/&quot;&gt;Habana Gaudi Intel&lt;/a&gt;&lt;/li&gt;
&lt;/ul&gt;
&lt;h3&gt;Part 2&lt;/h3&gt;
&lt;ul&gt;
&lt;li&gt;&lt;a href=&quot;https://github.com/amd/Kria-RoboticsAI&quot;&gt;Getting started setup&lt;/a&gt;&lt;/li&gt;
&lt;/ul&gt;
</content:encoded></item></channel></rss>